1. Field of the Invention
The present invention relates to techniques for performing self-timing within a data processing apparatus.
2. Description of the Prior Art
Self-timing techniques are typically used to control certain systems that require knowledge of the period of their operation in order to schedule events based on the completion of that operation. A typical example of such a system is one where sense amplifiers are used, for example in Static Random Access Memory (SRAM) systems or other systems employing precharged structures. Power is supplied to a sense amplifier to enable it to sense any changes in the signals input to the sense amplifier, and to produce a particular output signal dependent on the changes in the input signals. In order to reduce power consumption, it is desirable to switch off the sense amplifiers as soon as they have evaluated any changes in their input signals and produced the corresponding output, since the sense amplifiers consume relatively high currents during their operation.
It will be appreciated by those skilled in the art that other forms of multistable circuits, other than sense amplifiers, may be employed to give rapid determination of outputs based on slow input data, and such circuits may use self-timed control in applications where power consumption is to be kept at a minimum, but in which output data must be determined as early as possible.
Self-timing is ususally achieved by having a series of additional reference components that operate in parallel to the system being self-timed and have identical output timing characteristics to it. However, the additional reference components are arranged such that, on evaluating their inputs, there is always a determinate reference transition. This reference transition may then by used, for example, either to indicate to other systems that the output data of the system is ready, or to control functional units within the system by, for example, disabling costly current-consuming sense amplifiers at the earliest opportunity.
There are two main disadvantages with the use of such additional reference components to perform the self-timing of the system. Firstly, the additional reference components required to perform the self-timing function take up space on the data processing circuit. Generally, when developing data processing circuits, there is a desire to keep the circuit as small as possible. The space that a circuity, such as an integrated circuit, occupies is at a premium. The smaller an integrated circuit is, the less expensive it will be to manufacture and the higher the manufacturing yield. For this reason, measures that reduce the size of an integrated circuit are strongly advantageous.
Secondly, by their very nature, the additional reference components performing the self-timing function will always be arranged to cause a transition in the signal output by those reference components. This process itself consumes power, and generally it is desirable to keep power consumption within a circuit as low as possible. It is becoming more commonplace for integrated circuits to be used in products which operate from battery power, such as portable laptop computers, mobile phones, personal organisers, etc. In such situations, it is clearly desirable to reduce the power consumption of these processing devices as much as possible, in order to improve the battery life of the products, i.e. the amount of time the products can be used for before needing to replace or recharge the batteries. However, it is not just in the area of battery powered products, where power consumption is a concern. The higher the power consumption, then the greater the heat generated by the integrated circuit. Hence, there is generally a desire to reduce power consumption wherever possible.
Hence, it is an object of the present invention to provide a data processing apparatus and method which is self-timed, but which consumes less power, and occupies less space, than the above described prior art self-timed data processing apparatus.